Heterogeneity aware shared DRAM cache for integrated heterogeneous architectures by Adarsh Patil

By: Contributor(s): Material type: TextTextPublication details: Bangalore IISc 2017Description: xv, 95pSubject(s): DDC classification:
  • 621.3973 P17 (THESIS)
Tags from this library: No tags from this library for this title. Log in to add tags.
Star ratings
    Average rating: 0.0 (0 votes)
Holdings
Item type Current library Call number Status Date due Barcode
Thesis Thesis JRD Tata Memorial Library 621.3973 P17 (THESIS) (Browse shelf(Opens below)) Not for loan T09433

Includes CD

IISc, Dept of CSA, MSc Thesis

There are no comments on this title.

to post a comment.

                                                                                                                                                                                                    Facebook    Twitter

                             Copyright © 2024. J.R.D. Tata Memorial Library, Indian Institute of Science, Bengaluru - 560012
                             Contact   Phone: +91 80 2293 2832