Heterogeneity aware shared DRAM cache for integrated heterogeneous architectures (Record no. 198420)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 00604nam a2200193Ia 4500 |
| 082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | 621.3973 |
| Item number | P17 (THESIS) |
| 100 ## - MAIN ENTRY--PERSONAL NAME | |
| Personal name | Patil, Adarsh |
| Dates associated with a name | |
| 245 ## - TITLE STATEMENT | |
| Title | Heterogeneity aware shared DRAM cache for integrated heterogeneous architectures |
| Statement of responsibility, etc. | by Adarsh Patil |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. | |
| Place of publication, distribution, etc. | Bangalore |
| Name of publisher, distributor, etc. | IISc |
| Date of publication, distribution, etc. | 2017 |
| 300 ## - PHYSICAL DESCRIPTION | |
| Extent | xv, 95p. |
| Accompanying material | |
| 500 ## - GENERAL NOTE | |
| General note | Includes CD |
| 500 ## - GENERAL NOTE | |
| General note | IISc, Dept of CSA, MSc Thesis |
| 653 ## - INDEX TERM--UNCONTROLLED | |
| Uncontrolled term | Heterogeneity; IHS architecture |
| 700 ## - ADDED ENTRY--PERSONAL NAME | |
| Personal name | Govindarajan, R |
| 919 ## - | |
| -- | 199018 |
| 950 ## - LOCAL HOLDINGS (RLIN) | |
| -- | |
No items available.
