Logic minimization algorithms for VLSI applications. (Record no. 10775)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 00498nam a2200157Ia 4500 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 240509b |||||||| |||| 00| 0 eng d |
| 082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | 005.1 N87 |
| 100 ## - MAIN ENTRY--PERSONAL NAME | |
| Personal name | Gurunath, B. |
| 245 ## - TITLE STATEMENT | |
| Title | Logic minimization algorithms for VLSI applications. |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) | |
| Place of publication, distribution, etc | Bangalore : |
| Name of publisher, distributor, etc | Indian Institute of Science, |
| Date of publication, distribution, etc | 1987. |
| 300 ## - PHYSICAL DESCRIPTION | |
| Extent | iv, 120 p. : |
| Other physical details | ill. |
| 500 ## - GENERAL NOTE | |
| General note | Includes references |
| 502 ## - DISSERTATION NOTE | |
| Dissertation note | PhD;1987;Electrical Communication Engineering |
| 700 ## - ADDED ENTRY--PERSONAL NAME | |
| Personal name | Advised by Biswas, Nripendra N. |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Koha item type | Thesis |
| Withdrawn status | Lost status | Source of classification or shelving scheme | Damaged status | Not for loan | Home library | Current library | Date acquired | Total Checkouts | Full call number | Barcode | Koha item type |
|---|---|---|---|---|---|---|---|---|---|---|---|
| Dewey Decimal Classification | JRD Tata Memorial Library | JRD Tata Memorial Library | 24/05/1996 | 005.1 N87 | T02521 | Thesis |
