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Design and implementation of a VLSI floating point arithmetic processor.

Rathna, G.N.

Design and implementation of a VLSI floating point arithmetic processor. - Bangalore IISc. 1990 - xiii, 144p - IISc., Dept. of EE, M.Sc. Thesis. .

Dewey Class. No.: 621.395 / N904 "THESIS"

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