A High-Performance Hardware Accelerator for Elliptic Curve Cryptography with Curve25519 and Curve448 /

Includes bibliographical references

MTech (Res) ; 2024 ; Electronic Systems Engineering

In modern critical infrastructures such as power grids, the security of data transmitted among diverse smart devices has become increasingly crucial with the widespread adoption of digital communication technologies while adhering to strict timing specifications. This necessitates the use of cryptographic hardware accelerators. We propose a novel high-performance hardware accelerator featuring a unified architecture designed to support Elliptic Curve Diffie-Hellman Key Exchange operations over NIST standard Montgomery Curves, Curve25519 and Curve448, offering 128-bit and 224-bit security levels, respectively. The accelerator optimizes performance through extensive parallel processing and restructuring of arithmetic operations in the Montgomery Ladder while minimizing area and power consumption by leveraging resource sharing between the two elliptic curves. It executes Karatsuba-style large-integer multiplications and exploits special mathematical properties of the underlying pseudo-Mersenne and Solinas prime fields for fast modular reduction operations. Our ASIC implementation synthesized in a 45 nm technology achieves exceptional execution times for Elliptic Curve Scalar Multiplication (ECSM) of 12.86 μs and 66.91 μs with energy consumption of 4.64 μJ and 24.12 μJ, for Curve25519 and Curve448, respectively, operating at a peak frequency of 80.71 MHz. Notably, our implementation demonstrates nearly two-fold improvement in ECSM performance compared to current state-of-the-art hardware solutions for Curve448. Additionally, the proposed design incorporates several standard countermeasures, including randomized projective coordinates, to mitigate potential timing and power side-channel attacks.