Investigations on voltage control of stacked dc-link Series capacitors with a nine-level Inverter for an induction motor load

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PhD; 2023; Electronic systems engineering

Multilevel Inverters offer several advantages over two-level inverters in applications involving medium voltage and high power levels. A variety of applications are now available for MLI technology, ranging from variable speed drives to high voltage DC (HVDC) applications, power factor correction, and renewable energy sources. The advantages of MLI include the use of devices with low voltage ratings, low switching losses, minimal electromagnetic interference, and low dV/dt stress for the solid state devices. Further, as the number of MLI increases, it o ers a nearly sinusoidal stepped phase voltage waveform with reduced harmonic content in the phase voltage. The most commonly used multilevel inverter topologies in literature are the neutral point clamp (NPC) MLI, flying capacitor (FC) based MLI and cascaded H-bridge (CHB) MLI. Extending the conventional three-level NPC to higher levels will increase the complexity of the NP voltage control requirement along with the requirement for a large number of power diodes. An increase in the number of levels using an FC topology not only increases the requirement for high voltage electrolytic capacitors, but also increases the complexity of balancing the capacitors' voltage during PWM switching cycles. CHB-based multilevel inverters have the disadvantage of requiring a greater number of DC power supplies. Another type of MLI is a hybrid-MLI, which is constructed by cascading NPC, FC, and CHB cells. A hybrid MLI serves one of a few purposes, which include a) increasing the level of inverter with a low switch count, b) reducing the voltage rating for the devices, and c) implementing di erent control balancing algorithms. In this thesis, Chapter 1 provides an overview of conventional two level inverters and their operation, basic MLIs and their operation, hybrid MLIs, and the implementation of PWM for MLIs. When an MLI is supplied from a single DC-link, the four-quadrant operation becomes much more convenient for motor drive loads. The problem lies in the use of high voltage devices by a low level MLI. Multiple capacitors stacked in series across a single DC-link and the resulting stacked MLIs are excellent options for enhancing level of the inverter and reducing the device voltage requirements. However, the main challenge remains the same as that of the NPC based inverter - the balancing of DC-link neutral points. Generally, NP voltage balancing technique fall into three categories: (a) the use of isolated DC-supplies for DC-link capacitors, (a) the use of external balancing circuits, and (b) cleverly operated/manipulated switching during PWM based on DC-link capacitor voltage conditions. Using isolated DC supplies is a conventional old method that makes a bulky inverter system. DC-link capacitor voltage balancing using external balancing circuits and manipulated switching during PWM focuses primarily on the average voltage balancing over a fundamental cycle for DC-link capacitors. In many topologies, neutral point voltage balancing is addressed by drawing zero average current from each NP within each 60◦ sector of a fundamental cycle. Therefore, these topologies need large DC-link capacitance to control the voltage ripple compared to the proposed topology. In this thesis, the DC-link capacitor voltage balancing is addressed by drawing zero instantaneous current from the NPs during the PWM operation. The first chapter also presents a mathematical model of the inverter with 'n' DC-link stacked series capacitors for instantaneous voltage balancing. Practically, three NPs of four DC-link stacked series capacitors are balanced using six-phase and three phase IM loads. On excitation of motor phase terminals with opposite pole voltage, two opposite phases of a symmetrical six-phase IM generate 180◦ opposite phase currents. These opposite phases are forced to be connected to a single NP by means of low voltage CHBs. A generalised MLI for instantaneous NP voltage balancing using a six-phase load is presented in detail in Chapter 2. This chapter concludes with detailed results on a ninelevel inverter prototype designed for instantaneously balancing four DC-link capacitor voltage. The DC-link capacitor voltage balancing algorithm is also tested for steadystate and transient conditions using the six-phase IM load and the nine-level hybrid inverter. The third chapter examines the same concepts as chapter two, but with a three-phase IM load. The discussion of instantaneous voltage balancing for a general MLI structure with 'n' DC-link series connected capacitor is continued for a three phase load. In contrast with chapter 2, in this case all three phases are connected to a single NP or DC-link bus terminal during the PWM operation by means of low voltage CHBs. It ensures that iA+iB +iC = 0 for any DC-link NP, and that the DC-link capacitors are instantaneously balanced. A nine-level hybrid inverter prototype is used to demonstrate the selection of pole-voltage redundancy, space vector redundancy for NP voltage balancing, and nominal voltage level control for CHB capacitors. The detailed experimental results for the steady and transient condition are also presented at the end of this chapter. There is no discussion in these two chapters above regarding the DC-link capacitor voltage deviation or disturbance control during steady state or transient PWM operation. If there is a disturbance in the DC-link NP, the PWM operation will be continued with that disturbed NP. In the next work of Chapter four, the same nine-level inverter prototype is used to control DC-link capacitor voltage deviations using the phase currents of a three-phase load. A control algorithm is provided that regulates the DC-link NP voltage deviation, instantaneous voltage balancing for already balanced NPs, and thereafter maintaining the nominal voltage of the CHB capacitors. The results of intentional charging-discharging and control of DC-link NPs are presented at the end of Chapter 4, for different loads that cover both low and high power factors load conditions. The last and final chapter examines the limitations of nine-level inverters, discussed in chapter 3 for instantaneous NP voltage balancing. An extended linear modulation range or linear over-modulation is attempted for a three phase IM load. It has been seen that the linear modulation range (LMR) can be increased to full base speed even for loads with high power factors. The same topology of instantaneous NP voltage balancing is also tested under load unbalanced conditions. The works discussed in Chapters 2 to 6 have been first coded and simulated in MATLAB. Every control algorithm from each chapter has been tested using a resistive inductive load (RL load). The load is designed to draw 10 kW of power under all power factor conditions and frequencies. The hardware experiments share a common controller platform. A DSP (TMS320F28335) and an FPGA (Xilinx Spartan 3 XC3S400) are used to implement the control actions in these chapters. The ADC block in DSP sense the CHB capacitors' voltages and phase currents. The number of samples per fundamental cycle is chosen such that a minimum 1 kHz and maximum 2 kHz switching frequency of the inverter is ensured at all modulation indexes. The laboratory prototype is built using o -the-shelf devices. SKM75GB123D IGBTs for the stacked inverter of each phase, and IRF260N MOSFET switches for the CHB inverter cells, 4.7 mF, 250 V for CHB capacitors, and 3.3 mF, 200 V for DC-link capacitors are used to build the prototype. The advantages of this voltage control technique for NPs are: 1) a single dc link at the source makes the topology suitable for four-quadrant medium-voltage motor drive applications; 2) low-voltage series-connected dc-link capacitors can be replaced by battery cells for EV applications; 3) inherent voltage control of the batteries is possible using the switching state redundancies and the load phase currents, and no external circuit is required for voltage balancing of these battery cells. Moreover, the proposed balancing technique is general in nature and more dc-link series capacitors can added to extend the level for MLI, which can be realized using low-voltage switching devices.