Systematic approach to synthesis of verification test-suites for modular SoC designs by Sudhakar Surendran

By: Material type: TextTextSeries: IISc., Dept of SERC, MSc ThesisPublication details: Bangalore Indian Institute of Science 2006Description: xiii, 221pSubject(s): DDC classification:
  • 621.381530287 P06 "THESIS"
Tags from this library: No tags from this library for this title. Log in to add tags.
Star ratings
    Average rating: 0.0 (0 votes)
Holdings
Item type Current library Call number Status Date due Barcode
Thesis Thesis JRD Tata Memorial Library 621.381530287 P06 "THESIS" (Browse shelf(Opens below)) Not for loan T06251

CD included

There are no comments on this title.

to post a comment.

                                                                                                                                                                                                    Facebook    Twitter

                             Copyright © 2024. J.R.D. Tata Memorial Library, Indian Institute of Science, Bengaluru - 560012
                             Contact   Phone: +91 80 2293 2832