Towards a Generalized Approach in Design-for-Testability for Analog & Mixed-Signal ICs /

Includes bibliographical references

PhD ; 2024 ; Electrical Communication Engineering

The increasing complexity of analog and mixed-signal integrated circuits (AMS ICs) poses significant challenges in ensuring their reliability and functionality through effective testing methodologies. Traditional design-for-testability (DfT) techniques, primarily tailored for digital circuits, often fall short in addressing the unique requirements of AMS designs. This thesis presents a novel, generalised approach to DfT specifically developed for AMS ICs with a focus on reducing overhead during post-silicon validation and as an upgrade to the existing DfT techniques for digital ICs. The thesis begins with an introduction to IC testing practices, covering topics like Automatic Test Equipment (ATE), key testing metrics, and types of tests. It also discusses trends, challenges, and advancements in mixed-signal DfT, concluding with the problem statement and key contributions of the thesis. After a brief overview, a comprehensive study of existing DfT techniques is conducted, with a particular focus on methods that offer minimal overhead, such as alternate testing. The workthen introduces a Machine Learning-based Regression Model (MLRM) and a novel Analog Probe Module (APM) to improve IC testing efficiency and accuracy. First, a generalised framework based on MLRM is proposed to accelerate post-silicon validation for AMS-ICs by leveraging simulation data from earlier design stages. A 180nm RF CMOS LC-Voltage Controlled Oscillator (LC-VCO) from a radar-on-chip system is used as a case study. MLRM is employed to establish a relationship between internal DCnode voltages and performance metrics, enabling the prediction of the LC-VCO’s tuning curve during testing. Based on the success of the case study, an Analog Probe Module (APM), a compact on-chip solution for probing multiple internal IC nodes, is introduced. Anovel and highly optimised layout, along with the concept of a State Transition Matrix (STM), is incorporated to minimise glitches in asynchronous circuits and improve DfT integration. Atest chip is designed to validate the APM’s functionality. An alternative test method based on APM-based measurement of internal DC node voltages is proposed, and its application in predicting process-corner characteristics of on-chip circuits is demonstrated. The proposed APM-based methodology is benchmarked against industry-standard methods using 16 fabricated ICs. The method’s effectiveness in predicting IC’s process corner disposition (and hence its performance metrics) using simple data analysis techniques is evaluated. The thesis concludes by summarising the key contributions, including the development of MLRM for post-silicon validation, the design of the compact APM, and the successful demonstration of corner prediction. Potential future research directions are also outlined. By integrating both traditional DfT strategies and advanced techniques tailored to the analog domain, the proposed methodology enhances fault detection capabilities and overall test time reduction. This approach not only improves testability but also aligns with the constraints of modern IC design processes, thus providing a comprehensive solution to the challenges of AMS IC testing. The effectiveness of the proposed methodology is demonstrated throughout this thesis through case studies and experimental results, illustrating its potential to significantly advance the field of AMS IC design and testing