Transistor design methodology for sub 100 nm CMOS technology in presence of gate oxide leakage by Kingsuk Maitra

By: Material type: TextTextSeries: IISc, Dept of ECE, MSc(Engg) thesisPublication details: Bangalore Indian Institute of Science 2002Description: xi, 61pSubject(s): DDC classification:
  • 621.381528 P02 "THESIS"
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Item type Current library Call number Status Date due Barcode
Thesis Thesis JRD Tata Memorial Library 621.381528 P02 "THESIS" (Browse shelf(Opens below)) Not for loan T05176

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