Automatic generation of compiled cycle level microarchitecture simulators for superspeculative processors by Priya Chandran

By: Contributor(s): Material type: TextTextPublication details: Bangalore: Indian Institute of Science, 2004.Description: xvi, 256 pDDC classification:
  • 004.160113 P04 "THESIS"
Dissertation note: PhD;2004;Supercomputer Education and Research Centre
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Item type Current library Call number Status Date due Barcode
Thesis Thesis JRD Tata Memorial Library 004.160113 P04 (Browse shelf(Opens below)) Not for loan T05737

Includes bibliographical references

PhD;2004;Supercomputer Education and Research Centre

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