Ghosh, Debabrata <br/><br/>
Methodology to design performance - driven multipliers using normal process complementary pass transistor logic (NPCPL)   
by Debabrata Ghosh 
 - Bangalore  Indian Institute of Science  1992 
 - 146p 
 - IISc, Dept of EE, MSc Thesis .
<br/><br/><label>Dewey Class. No.: </label>621.395  / N9213 "Thesis"