TY  - BOOK
AU  - Patil, Adarsh
AU  - Govindarajan, R
TI  - Heterogeneity aware shared DRAM cache for integrated heterogeneous architectures
U1  - 621.3973 
PY  - 2017///
CY  - Bangalore
PB  - IISc
KW  - Heterogeneity; IHS architecture
N1  - Includes CD; IISc, Dept of CSA, MSc Thesis
ER  -