Patil, Adarsh   <br/><br/>
Heterogeneity aware shared DRAM cache for integrated heterogeneous architectures 
by Adarsh Patil 
 - Bangalore  IISc  2017 
 - xv, 95p.   
<br/><br/> Includes CD  IISc, Dept of CSA, MSc Thesis 
<br/><br/><label>Subjects--Index Terms: </label>Heterogeneity; IHS architecture 
<br/><br/><label>Dewey Class. No.: </label>621.3973  / P17 (THESIS)