Kala, S <br/><br/>
ASIC Implementation of a high throughput, low latency, memory optimized FFT processor   
by Kala S 
 - Bangalore  IISC  2012 
 - xiv, 81p 
 - IISc, Dept. of CeNSE, MSc Thesis .
<br/><br/> Includes CD 
<br/><br/><label>Dewey Class. No.: </label>621.384  / P12 "THESIS"