Ramesha, A <br/><br/>
Sub-threshold slope modeling and gate alignment issues in tunnel field effect transistor   
by A Ramesha 
 - Bangalore  IISC  2008 
 - vii, 36p 
 - IISc, Dept of CEDT (MSc) Thesis .
<br/><br/> CD enclosed 
<br/><br/><label>Dewey Class. No.: </label>621.381528  / P081 "THESIS"