Surendran, Sudhakar <br/><br/>
Systematic approach to synthesis of verification test-suites for modular SoC designs   
by Sudhakar Surendran 
 - Bangalore  Indian Institute of Science  2006 
 - xiii, 221p. 
 - IISc., Dept of SERC, MSc Thesis .
<br/><br/> CD included 
<br/><br/><label>Dewey Class. No.: </label>621.381530287  / P06 "THESIS"