Moitra, Kingsuk <br/><br/>
Transistor design methodology for sub 100 nm CMOS technology in presence of gate oxide leakage   
by Kingsuk Maitra 
 - Bangalore  Indian Institute of Science  2002 
 - xi, 61p. 
 - IISc, Dept of ECE, MSc(Engg) thesis .
<br/><br/><label>Dewey Class. No.: </label>621.381528  / P02 "THESIS"