Varaprasad, B.K.S.V.L. <br/><br/>
Efficient test pattern generation scheme for an on chip built in self test   
by B.K.S.V.L. Varaprasad 
 - Bangalore  Indian Institute of Science  2000 
 - xi,87p 
 - IISc, Dept of CEDT, MSc Thesis .
<br/><br/><label>Dewey Class. No.: </label>621.395011  / P "THESIS"