TY  - BOOK
AU  - Rathna, G.N.
TI  - Design and implementation of a VLSI floating point arithmetic processor
T2  - IISc., Dept. of EE, M.Sc. Thesis
U1  - 621.395 
PY  - 1990///
CY  - Bangalore
PB  - IISc.
ER  -