Rathna, G.N. <br/><br/>
Design and implementation of a VLSI floating point arithmetic processor. 

 - Bangalore  IISc.  1990 
 - xiii, 144p 
 - IISc., Dept. of EE, M.Sc. Thesis. .
<br/><br/><label>Dewey Class. No.: </label>621.395  / N904 "THESIS"