Algorithms for test generation and fault simulation of path delay faults in logic circuits by Ananta Kumar Majhi
Material type: BookSeries: I.I.Sc., Dept. of ECE., Ph.D., ThesisPublication details: Bangalore IISc 1996Description: vii, 116pSubject(s): DDC classification:- 621.395 N968 "THESIS"
Item type | Current library | Call number | Status | Date due | Barcode |
---|---|---|---|---|---|
Thesis | JRD Tata Memorial Library | 621.395 N968 "THESIS" (Browse shelf(Opens below)) | Available | T03954 | |
Reference | JRD Tata Memorial Library | 621.395 N968 "THESIS" (Browse shelf(Opens below)) | Available | G15528 |
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