Methodology to design performance - driven multipliers using normal process complementary pass transistor logic (NPCPL) by Debabrata Ghosh

By: Material type: BookBookSeries: IISc, Dept of EE, MSc ThesisPublication details: Bangalore Indian Institute of Science 1992Description: 146pSubject(s): DDC classification:
  • 621.395 N9213 "Thesis"
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Item type Current library Call number Status Date due Barcode
Thesis Thesis JRD Tata Memorial Library 621.395 N9213 "Thesis" (Browse shelf(Opens below)) Available T03325

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