Amazon cover image
Image from Amazon.com

Hiearchial modeling for VLSI circuit testing by Debashis Bhattacharya and Jhon P Hayes

By: Contributor(s): Material type: BookBookSeries: Kluwer international series in engineering and computer science VLSI, computer architecture and digital signal processing ; Publication details: Boston KAP 1990Description: x, 159pISBN:
  • 079239058X
Subject(s): DDC classification:
  • 621.3950287 N90
Tags from this library: No tags from this library for this title. Log in to add tags.
Star ratings
    Average rating: 0.0 (0 votes)
Holdings
Item type Current library Call number Status Date due Barcode
Reference Reference JRD Tata Memorial Library 621.3950287 N90 (Browse shelf(Opens below)) Available 144824

There are no comments on this title.

to post a comment.

                                                                                                                                                                                                    Facebook    Twitter

                             Copyright © 2023. J.R.D. Tata Memorial Library, Indian Institute of Science, Bengaluru - 560012
                             Contact   Phone: +91 80 2293 2832

Powered by Koha