Sub-threshold slope modeling and gate alignment issues in tunnel field effect transistor by A Ramesha

By: Material type: BookBookSeries: IISc, Dept of CEDT (MSc) ThesisPublication details: Bangalore IISC 2008Description: vii, 36pDissertation: Subject(s): DDC classification:
  • 621.381528 P081 "THESIS"
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Item type Current library Call number Status Date due Barcode
Thesis Thesis JRD Tata Memorial Library 621.381528 P081 "THESIS" (Browse shelf(Opens below)) Available T06663

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