Efficient test pattern generation scheme for an on chip built in self test by B.K.S.V.L. Varaprasad

By: Material type: BookBookSeries: IISc, Dept of CEDT, MSc ThesisPublication details: Bangalore Indian Institute of Science 2000Description: xi,87pSubject(s): DDC classification:
  • 621.395011 P "THESIS"
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Item type Current library Call number Status Date due Barcode
Reference Reference JRD Tata Memorial Library 621.395011 P "THESIS" (Browse shelf(Opens below)) Available G15687

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