Fault creation, detection and classification systems for modern power grids / (Record no. 433387)
[ view plain ]
| 000 -LEADER | |
|---|---|
| fixed length control field | 06201nam a2200313 4500 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 250408b |||||||| |||| 00| 0 eng d |
| 041 ## - LANGUAGE CODE | |
| Language code of text/sound track or separate title | en |
| 082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | 621.3192 |
| Item number | RAJ |
| 100 ## - MAIN ENTRY--PERSONAL NAME | |
| Personal name | Rajesh, K B |
| 245 ## - TITLE STATEMENT | |
| Title | Fault creation, detection and classification systems for modern power grids / |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) | |
| Place of publication, distribution, etc | Bangalore : |
| Name of publisher, distributor, etc | Indian Institute of Science, |
| Date of publication, distribution, etc | 2024. |
| 300 ## - PHYSICAL DESCRIPTION | |
| Extent | xxxv, 232 p. : |
| Other physical details | col. ill. |
| Accompanying material | e-Thesis |
| Size of unit | 13.66 Mb |
| 500 ## - GENERAL NOTE | |
| General note | Includes bibliographical references |
| 502 ## - DISSERTATION NOTE | |
| Dissertation note | PhD;2024;Electrical Engineering |
| 520 ## - SUMMARY, ETC. | |
| Summary, etc | The power grid is changing with the exponentially growing penetration of inverter-based resources (IBRs). Keeping the power grid stable, reliable, and secure, and delivering quality power has become increasingly important in recent years. As a result, many countries have devised grid codes for operating IBRs. Grid codes specify the requirements for IBRs to stay connected to the grid during various grid conditions, such as short circuit faults. As a result, a variety of devices are being developed to create grid short-circuit fault conditions. In addition to validating grid codes, devices capable of generating accurate and realistic fault transients are highly desirable for developing effective protection countermeasures, testing relay algorithms, studying fault characteristics in IBRs, and performing parameter estimation of power system components. Existing converter-based fault creators require high bandwidth control to provide an adjustable transient recovery voltage (TRV) feature. Providing this feature in the existing PWFCs utilizing FQSes is also difficult due to multiple over-voltage clamping circuits. The time series data generated during faults in power systems is essential for the development and validation of data-driven algorithms for power systems anomaly detection, classification, and mitigation. This thesis explores the design of a point-on-wave fault creator (PWFC) with an adjustable transient recovery voltage feature. The developed PWFC can create all types of balanced and unbalanced faults at any desired angle on the voltage waveform (point-on-wave). Over-voltage protection is essential for solid-state switches in fault creators while clearing the fault. Existing fault creators using FQS, use one or two capacitors/surge protection devices per FQS for over-voltage protection. Hence, fault creators with ‘N’ FQSes need ‘N’ or ‘2N’ capacitors, which increases the number of capacitors used in the fault creator, making it costly and bulky. In contrary to this, the PWFC topology in the author’s M-tech project uses a single capacitor to protect all FQSes from overvoltage. A systematic analytical procedure to select the single capacitor value, adjustable transient recovery voltage feature, and a finite state machine (FSM) for PWFC control is developed in this thesis. The performance of the FQS and the PWFC are investigated under a wide range of test scenarios, including thermal considerations and parasitic components. The ability of the selected capacitor to protect the FQSes during all types of fault clearances is experimentally validated by creating faults in an experimental test bed using the PWFC prototype. A novel FQS topology is proposed that can be realized using two commercially available half-bridge semiconductor modules. With this unique method of FQS realization, the lowest package count (Two), lowest on-state drop (one active switch plus one diode), modularity and scalability of the structure, gate control, and minimal package inter-connection length are simultaneously achieved. An adjustable TRV feature is achieved using a variable output voltage pre-charge circuit as a cost-effective solution. An algorithm is proposed to obtain the initial capacitor voltage required to limit the TRV to a specified target value. The experimental results demonstrated the ability of the PWFC to adjust the TRV for all fault configurations as per the test requirements. A combined fault and power quality disturbance detection and classification method using symbolic dynamic filtering (SDF) is also developed. An SDF is constructed based on the symbolic encoding of time series data and finite state automata to generate steady state probability distribution vectors (histograms) as signature patterns for different fault categories and power quality events. It provides an edge over existing methodologies as it compresses voluminous fault data into fixed-length probability distributions, which serve as the feature vectors for classifiers. Irrespective of the length of the time series data or the number of coefficients of the transformation used, the feature vector’s length is fixed in SDF. A new sinusoidally distributed partitioning (SDP) scheme is proposed for symbolic encoding. The proposed methodology can detect and classify low-impedance faults, high impedance faults, and power quality disturbances. Support vector machines and k-nearest neighbor classifiers are explored for fault classification using the histograms. The proposed methodology is tested on two active distribution systems, the modified IEEE 33 and 13 bus systems. In addition to fault detection and classification, a data-driven method is proposed to identify the hardware signature of Intelligent Electronic Devices (IED) used in power grids. It utilizes test function data of the analog-to-digital converter (ADC) used in the IED. A credit card-sized Parallella board and ADC of a custom IED platform are utilized to obtain the hardware signature. A finite state machine is developed in the FPGA of the Parallella processor to control the ADC for generating different data sets to extract signature.<br/>URI |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Power system faults |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Four quadrant switch |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Ever voltage protection |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Transient thermal model |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Symbolic dynamic filtering |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Hardware signature |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Inverter-based resources |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Point-on-wave fault creator |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Transient recovery voltage |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Capacitor |
| 700 ## - ADDED ENTRY--PERSONAL NAME | |
| Personal name | Advised by Gurrala, G |
| 856 ## - ELECTRONIC LOCATION AND ACCESS | |
| Uniform Resource Identifier | https://etd.iisc.ac.in/handle/2005/6851 |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Koha item type | Thesis |
No items available.
