Multi core memory system design: Developing and using analytical models for performance evaluation (Record no. 193495)
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000 -LEADER | |
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fixed length control field | 00602nam a2200169Ia 4500 |
082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER | |
Classification number | 004.252 P15 |
100 ## - MAIN ENTRY--PERSONAL NAME | |
Personal name | Dwarakanath, Nagendra Gulur |
245 ## - TITLE STATEMENT | |
Title | Multi core memory system design: Developing and using analytical models for performance evaluation |
Statement of responsibility, etc | by Dwarakanath Nagendra Gulur |
260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) | |
Place of publication, distribution, etc | Bangalore: |
Name of publisher, distributor, etc | Indian Institute of Science, |
Date of publication, distribution, etc | 2015. |
300 ## - PHYSICAL DESCRIPTION | |
Extent | xxiv, 237p. : |
500 ## - GENERAL NOTE | |
General note | Includes CD and bibliographical references |
502 ## - DISSERTATION NOTE | |
Dissertation note | PhD;2016;Supercomputer Education and Research Centre |
700 ## - ADDED ENTRY--PERSONAL NAME | |
Personal name | Advised by R. Govindarajan |
852 ## - LOCATION/CALL NUMBER | |
Piece designation | G27186 |
942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
Koha item type | Thesis |
Withdrawn status | Lost status | Source of classification or shelving scheme | Damaged status | Not for loan | Home library | Current library | Date acquired | Total Checkouts | Full call number | Barcode | Koha item type |
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Dewey Decimal Classification | JRD Tata Memorial Library | JRD Tata Memorial Library | 27/08/2016 | 004.252 P15 | T08714 | Thesis |