Efficient Design Of Embedded Data Acquisition Systems Based On Smart Sampling (Record no. 191683)

MARC details
000 -LEADER
fixed length control field 00604nam a2200193Ia 4500
082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER
Classification number 621.398140723
Item number P14 "THESIS"
100 ## - MAIN ENTRY--PERSONAL NAME
Personal name Satyanarayana, J V
245 ## - TITLE STATEMENT
Title Efficient Design Of Embedded Data Acquisition Systems Based On Smart Sampling
Statement of responsibility, etc. by J V Satyanarayana
260 ## - PUBLICATION, DISTRIBUTION, ETC.
Place of publication, distribution, etc. Bangalore
Name of publisher, distributor, etc. IISc
Date of publication, distribution, etc. 2014
300 ## - PHYSICAL DESCRIPTION
Extent xxxii, 178p
490 ## - SERIES STATEMENT
Series statement IISc Dept. of EE PhD Thesis
Volume/sequential designation
500 ## - GENERAL NOTE
General note Includes CD
690 ## - LOCAL SUBJECT ADDED ENTRY--TOPICAL TERM (OCLC, RLIN)
Topical term or geographic name as entry element Analog to Digital Conversions; Embedded Data Acquisition Systems; Smart-Sampling Data Acquisition
919 ## -
-- 192257
Holdings
Withdrawn status Lost status Damaged status Not for loan Home library Current library Date acquired Total Checkouts Full call number Barcode Koha item type
        JRD Tata Memorial Library JRD Tata Memorial Library 17/02/2016   621.398140723 P14 "THESIS" T08438 Thesis

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