Logic Synthesis and Verification Algorithms (Record no. 154930)
[ view plain ]
| 000 -LEADER | |
|---|---|
| fixed length control field | 00604nam a2200193Ia 4500 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| International Standard Book Number | 0306475928 |
| 082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | 621.39/5 |
| Item number | |
| 100 ## - MAIN ENTRY--PERSONAL NAME | |
| Personal name | Hachtel, Gary D. |
| Dates associated with a name | Somenzi, Fabio |
| 245 ## - TITLE STATEMENT | |
| Title | Logic Synthesis and Verification Algorithms |
| Remainder of title | |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. | |
| Name of publisher, distributor, etc. | Kluwer Academic Publishers |
| Date of publication, distribution, etc. | 1996. |
| 300 ## - PHYSICAL DESCRIPTION | |
| Extent | 597 Pages |
| 690 ## - LOCAL SUBJECT ADDED ENTRY--TOPICAL TERM (OCLC, RLIN) | |
| Topical term or geographic name as entry element | Computer-aided design., Integrated circuits -- Verification.; |
| 919 ## - | |
| -- | 162737 |
| 964 ## - | |
| -- | |
| -- | |
| -- | |
| -- | |
| -- | |
| -- | |
| -- | WFILEX |
No items available.
